 Virtuoso UltraSim Full-chip Simulator vMMSIM培訓(xùn) |
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近開課時(shí)間(周末班/連續(xù)班/晚班）：Virtuoso UltraSim Full-chip Simulator vMMSIM培訓(xùn)：2025年12月15日..以質(zhì)量求發(fā)展....合作共贏....實(shí)用實(shí)戰(zhàn).....直播、現(xiàn)場培訓(xùn)皆可....用心服務(wù)..........--即將開課--...............................(歡迎您垂詢，視教育質(zhì)量為生命！) |
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Virtuoso UltraSim Full-chip Simulator vMMSIM培訓(xùn)
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Course Description
In this course, you run FastSPICE simulation on large, complex, mixed-signal designs using the Virtuoso? UltraSim Full-chip Simulator. You explore the capabilities, methods, and modes of the simulator. You apply a variety of configurations that exploit the simulator's commands and options. You gain experience with hierarchical simulations, simulations of individual blocks, aged simulations, and EMIR analysis.
Learning Objectives
After completing this course, you will be able to:
- Simulate complex mixed-signal circuits quickly, using the FastSPICE simulator and Virtuoso UltraSim Full-chip Simulator
- Adjust the simulator's option settings to produce the proper tradeoff between accuracy and speed
- Construct probes and measures for reporting circuit performance during simulation
- Examine postprocessing measurement
- Verify the circuit performance and identify the potential failure modes by running advanced analysis, including static and dynamic checks
- Run hierarchical top-level simulations for prelayout, combining transistor-level schematics with structural Verilog? HDL, behavioral Verilog-A models, or behavioral Verilog HDL models, digital stimulus (.vec, .vcd) files and postlayout simulation with adjustable parasitic reduction
- Analyze the potential IR drop and electromigration (EM) problems in the layout by using Power IR/EM option and netlist-based EMIR
- Effectively use the integration of FastSPICE simulation in the Analog Design Environment to improve silicon accuracy and time-to-market
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