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?SystemVerilog Verification Using VMM Methodology

OVERVIEW

In this hands-on workshop, you will learn how to develop a VMM SystemVerilog test environment structure which can implement a number of different test cases with minimal modification. Within this VMM environment structure, you will develop stimulus factories, check and coverage callbacks, message loggers, transactor managers, and data flow managers. Once the VMM environment has been created, you will learn how to easily add extensions for more test cases.
After completing the course, you should have developed the skills to write a coverage-driven random stimulus based VMM testbench that is robust, re-useable and scaleable.

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OBJECTIVES

At the end of the course you should be able to:

??Develop an VMM environment class in SystemVerilog?
??Implement and manage message loggers for printing to terminal or file?
??Build a random stimulus generation factory?
??Build and manage stimulus transaction channels?
??Build and manage stimulus transactors
??Implement checkers using VMM callback methods?
??Implement functional coverage using VMM callback methods

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AUDIENCE PROFILE

Design or Verification engineers who develop SystemVerilog testbenches using VMM base classes.

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PREREQUISITES

To benefit the most from the material presented in this workshop, students should:

Have taken the SystemVerilog Testbench workshop

OR

Possess equivalent knowledge of SystemVerilog testbench including:
??Creating/Using SystemVerilog interfaces?
??How to encapsulate testbench components in SystemVerilog class structure
??Familiarity with SystemVerilog class inheritance
??Creating/Using System Verilog queues?
??Creating Cover Group for functional coverage

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COURSE OUTLINE

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Unit 1?
??SystemVerilog class inheritance review
??VMM Environment?
??Message Service
??Data model

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Unit 2
??Stimulus Generator/Factory?
??Check & Coverage
??Transactor Implementation?
??Data Flow Control?
??Scenario Generator?
??Recommendations