?使用 SystemVerilog 進行設(shè)計培訓Designing with SystemVerilog

Who Should Attend?

FPGA designers and logic designers

Course Outline

?1

• Introduction to SystemVerilog
• Data Types
• Lab 1:?SystemVerilog Data Types
• Structures, Unions, and Arrays
• Additional Operators in System Verilog
• Procedural Statements and Flow Control
• Lab 2:?always_ff and always_comb Procedural Blocks

?2

• Functions, Tasks, and Packages
• Interfaces
• Lab 3:?Interfaces and Design Download
• Packages
• Targeting Xilinx FPGAs